1. Field of the Invention
The present invention relates to a semiconductor device operating in synchronization with a clock, and particularly relates to a semiconductor device configured to control operation timings in accordance with latencies.
2. Description of Related Art
In recent years, synchronous semiconductor memory devices operating in synchronization with a clock have been advanced to operate at a higher speed. For example, since extremely high data transfer rate is required in DRAM represented by DDR3-SDRAM (Double Data Rate 3 Synchronous Dynamic Random Access Memory), complication in circuit configuration and an increase in consumption current have become problems to be solved. This type of DRAM is provided with a latency counter circuit that counts the number of clock cycles as a latency from command issue to completion of data transfer during an operation. The latency counter circuit corresponding to a latency specification is required to include as a small number of circuit elements as possible and to be capable of operating with as small consumption current as possible. For example, Patent Reference 1 discloses a latency counter circuit having a configuration in which a command signal is sequentially latched using a clock obtained by dividing an external clock by two and a transmission path of the command signal can be selectively controlled in accordance with a preset latency for the purpose of counting the latency. By employing such a configuration, it is possible to achieve a latency counter circuit capable of obtaining operating margin when counting a user-set desired latency with a high speed.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2010-3397 (U.S. Pat. Nos. 7,715,272 and 7,864,623)
However, specifications of DDR3-SDRAM prescribe, for example, a CAS latency that takes values of a wide range from 5 clock cycles to 16 clock cycles. In order to count the latency of such a wide range, many flip-flops need to be implemented in the latency counter circuit. Further, since a command signal is transmitted through the many flip-flops, particularly when counting a large latency during a high-speed operation, an increase in charge/discharge currents for operating a high-speed clock is inevitable. The latency counter circuit in this case has a problem that it receives double penalties of an increase in circuit scale required for the operation and an increase in consumption current required during the high-speed operation. Further, there are a wide variety of latencies to be counted corresponding to operation modes in the DRAM other than the CAS latency, and therefore the circuit scale and the consumption current remarkably increase when providing latency counters corresponding to the respective latencies.